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Give two ways of converting a two input NAND gate to an inverter. |
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Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors) |
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Design a divide-by-3 sequential circuit with 50% duty circle. |
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Design any FSM in VHDL or Verilog. |
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Explain RC circuit’s charging and discharging. |
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Describe how you would reverse a singly linked list. |
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Give the truth table for a Half Adder. Give a gate level implementation of the same. |
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Draw a Transmission Gate-based D-Latch? |
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Give a circuit to divide frequency of clock cycle by two? |
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Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? |
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Describe how you would reverse a singly linked list. |
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How do you detect a sequence of "1101" arriving serially from a signal line? |
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What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit? |
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What is the difference between SYNONYM and ALIAS? |
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What are the different Adder circuits you studied? |
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The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this? |
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How do you detect if two 8-bit signals are same? |
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Draw a Transmission Gate-based D-Latch. |
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Explain RC circuit’s charging and discharging. |
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Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? |
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