|
Related Questions |
View Answer |
|
Explain RC circuit’s charging and discharging.
|
View Answer
|
|
Design any FSM in VHDL or Verilog.
|
View Answer
|
|
How do you detect a sequence of "1101" arriving serially from a signal line?
|
View Answer
|
|
How do you detect if two 8-bit signals are same?
|
View Answer
|
|
Design a Transmission Gate based XOR. Now, how do you convert it to XNOR?
|
View Answer
|
|
Draw a Transmission Gate-based D-Latch.
|
View Answer
|
|
Give the truth table for a Half Adder. Give a gate level implementation of the same.
|
View Answer
|
|
What are the different Adder circuits you studied?
|
View Answer
|
|
The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if you do this?
|
View Answer
|
|
Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of the combinational circuit is greater than your clock signal? (You can’t resize the combinational circuit transistors)
|
View Answer
|
|
Design a divide-by-3 sequential circuit with 50% duty circle.
|
View Answer
|
|
Give a circuit to divide frequency of clock cycle by two
|
View Answer
|
|
What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum clock frequency of a circuit?
|
View Answer
|
|
Given a circuit, draw its exact timing response.
|
View Answer
|
|
Give two ways of converting a two input NAND gate to an inverter.
|
View Answer
|