Question:
Instead of just 5-8 pipe stages why not have, say, a pipeline with 50 pipe stages?
Answer:
Source: CoolInterview.com
normally one stage of pipelining is completed in one clock cycle if we use 50 stages of pipelining then it takes 50 clock cycle to complete one instruction that decreases the speed of the execution of the instrution Source: CoolInterview.com
Answered by: a.vinupriya | Date: 3/11/2010
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The latency of the architecture increases with the pipeline stages. Penalty due to the flushing of the pipeline for instance will also increase Cycles Per Instruction of the CPU architecture Source: CoolInterview.com
Answered by: shantchandrakar | Date: 5/19/2010
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