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Related Questions |
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Draw the SRAM Write Circuitry
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What happens if we use an Inverter instead of the Differential Sense Amplifier?
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Draw the Differential Sense Amplifier and explain its working. Any idea how to size this circuit? (Consider Channel Length Modulation)
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Draw a 6-T SRAM Cell and explain the Read and Write operations
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For a NMOS transistor acting as a pass transistor, say the gate is connected to VDD, give the output for a square pulse input going from 0 to VDD
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Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
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Give the logic expression for an AOI gate. Draw its transistor level equivalent. Draw its stick diagram
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Given a layout, draw its transistor level circuit. (I was given a 3 input AND gate and a 2 input Multiplexer. You can expect any simple 2 or 3 input gates)
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In the design of a large inverter, why do we prefer to connect small transistors in parallel (thus increasing effective width) rather than lay out one transistor with large width?
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Why do we gradually increase the size of inverters in buffer design? Why not give the output of a circuit to one large inverter?
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What is Charge Sharing? Explain the Charge Sharing problem while sampling data from a Bus
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For CMOS logic, give the various techniques you know to minimize power consumption
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Draw the stick diagram of a NOR gate. Optimize it
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Let A & B be two inputs of the NAND gate. Say signal A arrives at the NAND gate later than signal B. To optimize delay, of the two series NMOS inputs A & B, which one would you place near the output?
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Draw a transistor level two input NAND gate. Explain its sizing (a) considering Vth (b) for equal rise and fall times
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What happens if we increase the number of contacts or via from one metal layer to the next?
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You have three adjacent parallel metal lines. Two out of phase signals pass through the outer two metal lines. Draw the waveforms in the center metal line due to interference. Now, draw the signals if the signals in outer metal lines are in phase with each other
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How does Resistance of the metal lines vary with increasing thickness and increasing length?
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What are the limitations in increasing the power supply to reduce delay?
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What happens to delay if we include a resistance at the output of a CMOS circuit?
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